PhD Intern- Scale System

Overview

Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer‑centric innovation and strong partnerships, we have established leading end‑to‑end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the world’s population.

With 20+ sites across Europe and 1500 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes our Research Center, located in Zurich, Switzerland. A major element of our Research Center is a rapidly growing research laboratory focused on fundamental research in the area of computing systems (new hardware, new software, new algorithms).

The research work of the lab will be carried out not only by Huawei’s internal research staff but also by our academic research partners in universities across Europe. The lab will provide an open research environment where academics will be encouraged to visit and work on fundamental long‑term research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such world‑leading scientific work.

• Conduct research on future large scale systems with a special emphasis on NoC topologies, memory hierarchies, and simulation/modeling.
• Collaborate closely with researchers and product teams to align models and simulations with real world constraints.
• Develop or extend analytical models and simulations to evaluate different architectures.
• Prepare whitepapers and academic publications.

• Currently enrolled in a PhD program in computer science, computer engineering, or electrical engineering.
• Deep knowledge of memory models, hierarchies, and coherence.
• Knowledge of CPU architecture, SoC design, and communication techniques desired.
• Experience with architectural simulation platforms for network‑on‑chip and systems‑on‑chip.
• Ability to evaluate existing literature and simulation platforms to implement and expand existing state‑of‑the‑art solutions.

• Currently enrolled in a PhD university program.
• Experience simulating and modeling large scale systems.
• Accepted papers or publications in conferences or journals on relevant topics.