Senior ASIC Layout Engineer

We’re seeking a Senior / Staff Custom Layout Engineer to join a cutting-edge semiconductor start-up. This permanent role offers the chance to work on next-generation compute-in-memory AI hardware, taking full ownership of transistor-level and block-level layout from floorplan to silicon while collaborating with cross-functional teams to drive performance, power, and yield improvements.

• Own full-custom layout for memory, mixed-signal, and custom-digital blocks from floorplan through sign-off.
• Implement device-level layouts with strong matching, symmetry, shielding, and isolation techniques.
• Plan macro floor plans, pins, abstracts, and tiling strategies for memory-like structures.
• Collaborate closely with schematic designers, digital teams, and backend engineers to meet aggressive performance, yield, and reliability targets.
• Close DRC, LVS, and PEX on advanced process nodes (sub-28 nm to leading-edge geometries).
• Integrate test structures, including scan wrappers, redundancy, and repair hooks.
• Develop layout automation scripts, templates, and documentation to support design efficiency.

• 6+ years of custom layout experience in analog, memory, or custom-digital IP.
• Proven ownership of blocks from floorplan to sign-off, ideally with tape-out experience on advanced nodes.
• Hands-on experience with FinFET, FDSOI, multi-patterning, EUV, or equivalent advanced processes.
• Strong analog layout skills: common-centroid/interdigitation, current-mirror symmetry, matched routing, shielding, guard rings, substrate isolation.
• Understanding of parasitic, timing, EM, and IR implications of layout; ability to interpret extraction reports and iterate designs.
• Engineering degree or equivalent in electronics, microelectronics, or related field.