Senior IC Layout Engineer Custom Analog/Mixed-Signal
Job in
Zürich, 8058, Zurich, Kanton Zürich, Switzerland
Listed on 2026-01-15
Listing for:
TalentCloud Group Recruitment
Full Time
position Listed on 2026-01-15
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer, Electrical Engineering
Job Description & How to Apply Below
Location: Zürich
Senior IC Layout Engineer
We are partnering with an innovative Zürich‑based tech company who are seeking a motivated Senior IC Layout Engineer, who enjoys full‑custom transistor‑level design and wants to help shape advanced silicon across modern process nodes. This is a full‑time permanently employed position.
What you’ll be doingThis is a hands‑on layout role with ownership from concept to tape‑out.
- ✏️ Creating full‑custom layouts at both transistor and block level
- 🧩 Working on mixed‑signal, custom‑digital, and memory‑adjacent layouts
- 🗺️ Planning floor plans and delivering DRC/LVS/PEX‑clean designs on advanced nodes
- 📐 Applying precision analog layout techniques (matching, symmetry, shielding, guarding, etc.)
- ⚡ Bridging analog craft with modern FinFET/FDSOI rules and multi‑patterning/EUV constraints
- 🤝 Collaborating closely with analog/custom designers, digital backend teams & verification engineers
- 🔁 Automating repetitive layout tasks using Python/Tcl (if you enjoy scripting)
- 📝 Maintaining guidelines, documentation & contributing to layout best practices
You will work on silicon that goes directly into cutting‑edge compute architectures – impact is immediate and visible.
әткә What you’ll bring- 5+ years in custom IC layout covering analog, memory, or custom‑digital blocks
- Experience delivering clean layouts on advanced nodes (sub‑28 nm, FinFET/FDSOI)
- Strong understanding of analog layout fundamentals:
- Current‑mirror symmetry
- Matching & shielding
- Guard rings & substrate isolation
- Ability to work confidently with design & backend teams on extraction, timing, IR & EM topics
- Familiarity with modern layout verification flows (DRC, LVS, PEX)
- Good communication, structured documentation habits & a collaborative mindset
- Experience with SRAM periphery, redundancy or memory‑adjacent layouts
- Knowledge of scan/MBIST routing or macro‑level integration
- Exposure to DFM/DFY, ESD/latch‑up, or EM/IR reliability checks
- Scripting experience in लड़ु or Python for automation
Position Requirements
10+ Years
work experience
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