Level Power and Mixed Signal Design Engineer

Overview

Staff Mixed Signal Design Engineer in the Platform IP Development group. Play a key role in architecting, developing, and supporting strategic analog and mixed‑signal IP that is delivered across multiple ADI products and application domains. This IP includes power management circuits such as LDOs, voltage monitors, precision references, oscillators, sensors, and related building blocks that serve as foundational platform elements used company‑wide.

You will blend deep analog expertise with system‑level awareness to create robust, reusable IP while collaborating closely with internal customers, cross‑functional design teams, layout, and validation. You’ll mentor junior designers, guide technical decisions, and contribute to continuous improvement in design methodologies for power and mixed‑signal IP. This position is well‑suited for someone who enjoys hands‑on design, cross‑team collaboration, and building high‑impact circuits that become part of ADI’s reusable technology foundation.

• Technical Design & Architecture – Lead the architectural definition and design of analog and mixed‑signal IP used in switching power domains, including LDOs, oscillators, references, sensors (current/voltage), and capless or low‑quiescent‑current topologies. Make informed architectural tradeoffs considering efficiency, noise, transient response, stability, parasitics, and system‑level constraints. Develop robust, reusable platform IP solutions optimized for wide integration across multiple SoCs, technologies, and applications.
• Verification & Silicon Validation – Perform detailed simulation verification, stability analysis, transient behavior studies, and robustness evaluations across PVT and system conditions. Guide and support characterization planning, bench debug, silicon bring‑up, and performance correlation. Ensure IP robustness through advanced analysis techniques and comprehensive verification strategies.
• Collaboration & Integration – Work closely with layout engineering to minimize parasitics, mitigate proximity effects, and ensure physical implementation meets design intent. Partner with internal customers (multiple products, business units, and applications teams) to define requirements, provide integration guidance, and support adoption of Platform IP. Document results clearly and lead technical reviews with cross‑functional teams.
• Leadership & Methodology Development – Mentor junior engineers in power‑domain circuit design, stability analysis, and silicon debug. Contribute to improving mixed‑signal and power design flows, including simulation, modeling, automation, and emerging AI‑assisted methodologies. Influence design best practices and help shape the evolution of platform IP strategy.

• Mixed‑Signal & Power Design Expertise:
  Strong foundation in designing power‑domain analog circuits such as LDOs, references, sensors, oscillators, and related blocks.
• System‑Level Thinking:
  Ability to understand integration across SoC boundaries and account for system interactions, parasitics, and performance sensitivities.
• Advanced Analysis Methods:
  Deep experience with stability analysis, noise optimization, efficiency tuning, and Monte Carlo/variability robustness.
• Verification Strength:
  Proficiency developing simulation plans, modeling complex behaviors, and validating circuits through silicon characterization.
• EDA Tool Mastery:
  Proficiency in SPICE‑based simulators, Cadence tools, and related design/verification environments.
• Collaboration & Communication:
  Demonstrated ability to work across teams, lead design reviews, communicate clearly, and navigate complex technical discussions with clarity and respect.
• Lab Debug
  
  Skills:
  
  Strong troubleshooting abilities and comfort working hands‑on with bench equipment and debug workflows.
• Project Leadership:
  Ability to lead IP efforts, drive schedules, and deliver production‑quality deliverables with minimal supervision.

• MSEE with 7‑10+ years of experience in analog/mixed‑signal IC design, or PhD with 5+ years of relevant experience.
• Proven track record of delivering power‑related analog/mixed‑signal IP to…