AI​/ML Applications Engineer - Product Validation & Test

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™.

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We are seeking a Staff Engineer to lead the application of AI‑enabled techniques to post‑silicon test, evaluation, and characterization across mixed‑signal and SoC products. This role sits within Engineering Enablement and is intended for a deeply experienced post‑silicon engineer who understands how silicon is actually evaluated in labs and on ATE—and who can strategically apply AI/ML and agentic tools to accelerate, scale, and improve those workflows.

This is a hands‑on, high‑impact individual‑contributor role with broad cross‑functional influence. You will define how AI is practically used in evaluation, characterization, calibration, trimming, and qualification—not as an abstract data science exercise, but as a tool to reduce measurement effort, improve insight, and shorten time‑to‑confidence in silicon.

• Identify high‑leverage opportunities where AI/ML can materially improve post‑silicon workflows, such as:
• Adaptive characterization (intelligent selection of next measurements)
• Anomaly detection in parametric, waveform, and RF data
• Measurement clustering and outlier identification
• Automated regression triage and silicon learning
• Calibration and trimming optimization
• Apply and integrate existing AI/ML technologies, including:
• Classical ML (clustering, regression, Bayesian methods)
• Time‑series and waveform analysis techniques
• Agentic AI systems for lab automation, test orchestration, and debug assistance
• Serve as a technical bridge between silicon/test engineers and:
• Internal ML specialists
• External vendors
• Academic or ecosystem partners
• Evaluate and prototype AI‑enabled tools for post‑silicon
• Develop reference workflows, guidelines, and examples for AI‑assisted evaluation and characterization.
• Create reusable frameworks that scale across products, nodes, and business units.
• Mentor engineers on:
• Modern post‑silicon data analysis techniques
• Practical use of AI tools in the lab and on ATE
• Represent the organization in Technical reviews, Vendor engagements, Industry forums

• 8+ years of hands‑on experience in post‑silicon test, evaluation, characterization, or validation of ASICs or SoCs.
• Deep practical experience with mixed‑signal and/or high‑speed digital blocks, such as:
• ADCs/DACs, PLLs, clocking
• SERDES, PHYs, high‑speed IO
• Power, timing, and signal‑integrity‑sensitive designs
• Strong understanding of:
• Silicon bring‑up
• Measurement instrumentation and data interpretation
• ATE‑based test and characterization flows
• Proven ability to debug silicon issues with limited observability and noisy data.
• Working knowledge of applying ML techniques to real measurement data, including Statistical modeling, Pattern recognition & Anomaly detection
• Experience using or integrating AI‑enabled tools in engineering workflows.
• Comfortable working in Python‑based analysis environments (not necessarily building ML frameworks).
• Ability to reason about data quality, bias, observability limits, and measurement noise—especially in analog/RF contexts.
• Strong cross‑functional communication skills; able to translate between silicon, test, and software/AI domains.
• Demonstrated technical leadership as a senior IC:
• Driving initiatives without direct authority
• Influencing methodology and direction
• Comfortable operating across abstraction levels—from waveform‑level analysis to system‑level implications.

• Experience with adaptive or data‑driven characterization, yield learning, or post‑silicon tuning.
• Exposure to reinforcement learning, Bayesian optimization, or active learning concepts applied…