Hybrid Design Verification Engineer; UVM/SystemVerilog
Job Description & How to Apply Below
A leading semiconductor manufacturer is seeking a Design Verification Engineer in Vancouver. This role requires expertise in digital design and verification, including duties such as writing test plans, developing test benches using System Verilog/UVM, and providing technical leadership. Candidates should possess a relevant degree and experience in ASIC design and related tools. This position offers a hybrid work environment and focuses on innovative engineering solutions within the semiconductor industry.
#J-18808-Ljbffr
Note that applications are not being accepted from your jurisdiction for this job currently via this jobsite. Candidate preferences are the decision of the Employer or Recruiting Agent, and are controlled by them alone.
To Search, View & Apply for jobs on this site that accept applications from your location or country, tap here to make a Search:
To Search, View & Apply for jobs on this site that accept applications from your location or country, tap here to make a Search:
Search for further Jobs Here:
×