Senior SoC Verification Engineer; UVM

Job Overview

Develop and maintain UVM-based verification environments for complex SoC projects.

Create comprehensive test plans, implement test cases, and ensure coverage closure.

Debug RTL and testbench failures using industry-standard simulators.

Collaborate closely with design, architecture, and firmware teams to ensure verification completeness.

Drive verification strategy from block-level to SoC-level integration.

Perform functional coverage analysis, assertion-based verification (SVA), and regression management.

Support post-silicon validation and bring-up activities as required.

• 6+ years of experience in ASIC/SoC verification.
• Strong hands‑on experience with System Verilog and UVM methodology.
• Proficiency in testbench architecture, stimulus generation, and scoreboard implementation.
• Experience with major EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Solid understanding of AMBA protocols (AXI/AHB/APB) and on‑chip interconnects.
• Familiarity with C/C++ and scripting languages (Python/Perl/Shell).
• Strong debug and problem‑solving skills.
• Excellent communication and teamwork abilities.

• Mid‑Senior level

• Contract

• Semiconductor Manufacturing

Location:

Tucson, AZ

Salary: $95,000.00 - $