Logic Design Engineer

Position: Staff Logic Design Engineer
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** Welcome!**## .Staff Logic Design Engineer page is loaded## Staff Logic Design Engineer locations:
Canada, Toronto time type:
Full time posted on:
Posted Todayjob requisition :
JR0280242#
** Job Details:**##

Job Description:

The key responsibilities of this person include the following:
* Logic design, register transfer level (RTL) coding, analog circuit behavioral modeling and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
* Participating in the definition of architecture and microarchitecture features of the block being designed.
* Applying various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
* Reviewing the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
* Supporting SoC customers to ensure high quality integration and verification of the IP block.
* Driving quality assurance compliance for smooth IP SoC handoff.
* Create design documentation

The Logic Design Engineer should possess the following attributes:
* Excellent communication:
Expected to drive clarity across partners, managers.
* Excellent teamwork:
With a relatively small team, we need everyone to help however and wherever they can.
* Strong analytical and problem-solving skills with the skills to independently draw conclusions.##
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* Qualifications:

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* Minimum qualifications:

Bachelor's degree in Electrical/Computer Engineering with 8+ years of combined experience
** OR
* * Master's degree in Electrical/Computer Engineering with 6+ years of combined experience in:
* Mixed-signal design, specifically High-Speed Ser Des design and architecture
* Experience with PCS/FEC, gearbox, equalization, and clocking structures
* Experience with pipelining, retiming, clock domain crossings (CDC), and latency optimization
* Experience with post-silicon validation and support of High-Speed Ser Des IP
* Experience working with automated Place-and-Route (APR) teams on synthesis, STA constraints, timing closure, and DFT considerations
* Knowledge of FFE/DFE filters, CDR DSP blocks, interpolation/decimation, and adaptive algorithms
* Reading and interpreting technical specifications to develop microarchitecture and implement RTL design in System Verilog
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* Preferred Qualifications:

*** Familiarity with AXI, AHB, and APB protocols
* DSP-based CDR design, Forward Error Correction (FEC) coding, hardware/software co-simulation, power/performance optimization, and machine learning-assisted DSP tuning
* Experience with PCIe, Ethernet (100G/400G/800G), CEI, USB, or similar standards
* Scripting proficiency in at least one interpreted language (e.g., TCL, Perl, Python, Ruby)
* Knowledge of UVM/testbench architecture, constrained random testing, and functional coverage## Job Type:Experienced Hire##

Shift: Shift 1 (Canada)## Primary

Location:

Canada, Toronto## Additional Locations:## Business group:

Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges.

Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.## Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other…