FPGA Design Engineer

We’re hiring a Staff FPGA Design Engineer to help combine deep chip design expertise with machine learning to build intelligent, end-to-end silicon design flows that move from research to production.

Serve as FPGA/RTL domain expert for AI-driven chip design assistants

Architect modern EDA workflows (spec to bitstream)

Enable AI agents to generate correct-by-construction RTL, manage IP, and build processor-based systems

Develop libraries, tools, datasets, and benchmarks to accelerate design velocity

Define strong verification standards and guide AI-generated UVM environments

Master’s in Electric Engineering, Computer Science or related field

10–15 years of RTL design and/or verification experience

Deep expertise in Xilinx (Vivado/Vitis) and Intel/Altera (Quartus) ecosystems

Strong knowledge of AXI, PCIe, Ethernet, NoC, DDR5,SPI, I2C

Proficiency in System Verilog, Python, TCL

Clear communicator comfortable in a fast-paced AI startup

Open-source contributions (Verilator, Cocotb, Yosys, OpenSTA)

Experience across full chip flow

Exposure to ML or deep learning

Past working experience for an AI startup

Have you worked with Xilinx Vivado or Vitis for FPGA design?

Have you worked with Intel/Altera Quartus for FPGA design?

Do you have 10+ years of RTL design or verification experience
?

Have you led an FPGA project from specification to bitstream or production silicon
?

Have you designed or integrated high-speed interfaces such as AXI, PCIe, Ethernet, DDR5, SPI, I2C, or NoC?

Have you used System Verilog for RTL design and/or verification?

Have you built or guided UVM-based verification environments
?

Have you automated FPGA workflows using Python or TCL scripts?

In a few lines, explain WHY YOU are an ideal fit for this Staff FPGA Design Engineer role.

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