Senior ASIC Digital Design Lead DDR IP
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2025-12-10
Listing for:
Synopsys Inc
Full Time
position Listed on 2025-12-10
Job specializations:
-
IT/Tech
Systems Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
A leading semiconductor company is seeking an ASIC Digital Design, Sr Manager to lead design teams in developing innovative DDR PHY IP solutions. The role requires extensive experience in Verilog and System Verilog, strong management skills, and the ability to navigate complex design processes. You will work closely with cross-functional teams to ensure project success and mentor engineers while fostering a culture of innovation.
This position offers a dynamic environment where strategic thinking and leadership are essential.
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Position Requirements
10+ Years
work experience
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