Senior PCB Layout Engineer

Senior PCB Layout Engineer

This role has been designed as “Onsite” with an expectation that you will primarily work from an HPE office.

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.

Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

A Senior PCB Layout Engineer is a technical expert responsible for designing complex, high-speed printed circuit boards using the Cadence Design Systems Allegro PCB Designer platform. This role focuses on advanced constraint-driven layout, signal integrity awareness, manufacturing readiness, and automation (often with SKILL), while leading critical hardware projects.

Design and deliver high-performance, multi-layer PCBs for complex electronic systems such as networking equipment, servers, telecom hardware, aerospace systems, or high-speed embedded platforms. The engineer works closely with hardware, SI/PI, mechanical, and manufacturing teams to ensure first-pass success and production readiness.

• Design complex boards (12–40+ layers) using Cadence Allegro PCB Designer
• Perform optimized component placement for:
  • High-speed digital
  • Power distribution
  • Thermal performance
  • EMI control
• Route critical interfaces:
  • DDR4/DDR5
  • PCIe Gen4/Gen5+
  • USB 3.x / Type-C
  • Ethernet (10G–112G Ser Des)
• Implement:
  • Differential pair routing and tuning
  • Length and phase matching
  • Controlled impedance structures

• Define and manage rules using Constraint Manager
• Develop stackups with controlled impedance and fabrication feasibility
• Work with PCB vendors to validate materials, via structures, and HDI capability

• Apply SI/PI best practices:
  • Return path continuity
  • Crosstalk reduction
  • Proper decoupling strategy
• Collaborate with SI/PI teams
• Implement simulation-driven layout changes

• Blind/buried vias and microvias
• BGA escape for high pin-count devices
• Back drilling for high-speed signals
• High-current and low-noise power routing

• Generate fabrication and assembly outputs:
  • ODB++, IPC-2581, Gerber
  • Drill files, drawings, stackup documentation
• Perform DFM/DFA reviews with vendors
• Support prototype builds and resolve manufacturing issues

• Mentor junior and mid-level PCB designers
• Lead layout planning and design reviews
• Estimate schedules and manage multiple projects

• 8–15+ years of PCB layout experience
• Expert proficiency in Cadence Allegro
• Strong knowledge of:
  • High-speed design techniques
  • Impedance control and stackup planning
  • HDI technologies
  • EMI/EMC fundamentals
• Solid understanding of PCB fabrication and assembly processes

• Networking, server, or telecom hardware experience
• Familiarity with:
  • 25G/56G/112G Ser Des
  • Backplane design
  • Thermal/mechanical co-design
• Experience with SI/PI analysis tools

• Enables first-pass board success (fewer respins)
• Supports higher data rates and system reliability
• Improves team efficiency through automation
• Serves as the technical authority for PCB layout

Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}