ASIC Implementation Lead

Google place Sunnyvale, CA, USA

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in silicon implementation with a focus on SoC or ASIC development.
• Experience leading cross-functional teams (PD, Package, Power, DFT) through the full tape-out cycle, from architecture to GDSII.
• Experience with advanced process nodes, packaging technologies, and the trade-offs between PPA, thermal, and signal integrity.
• Experience managing technical relationships with external vendors, ASIC partners, or foundries.

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 10 years of experience in silicon implementation with a focus on SoC or ASIC development.
• Experience with Customer Owned Tooling (COT) design models and the specific issues they present compared to traditional ASIC flows.
• Experience defining implementation roadmaps and influencing decisions at the system and architecture level.
• Experience articulating technical risks and status to executive management and cross-functional stakeholders.
• Ability to drive high-frequency/low-power chips to production with first-pass silicon success.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You’ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As the Implementation Technical Lead (TL), you are the technical captain responsible for the physical realization of our next-generation custom silicon. You will own the "implementability" of the entire chip, driving the convergence of Performance, Power, Area (PPA), thermal, and reliability specifications from architecture to tape-out. You will act as the primary bridge between disparate domains such as Physical Design, Packaging, Power, DFT, and Technology, unifying them into a cohesive execution strategy.

You will set the technical direction for internal teams and external vendors, ensuring that SoC systems are delivered on schedule with the highest quality.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We re behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

• Drive technical decisions and synchronization across all implementation domains (Physical Design, Package, Power, SI/PI,…