ASIC Power Engineer

We are seeking a highly experienced ASIC Power Engineer to support power analysis and optimization for next‑generation AR/VR silicon products. This role focuses on power, performance, and area (PPA) optimization across RTL and netlist levels, working closely with synthesis, physical design, and verification teams. The ideal candidate has strong expertise in low‑power methodologies, ASIC tool flows, and scripting for data analysis, with exposure to Machine Learning driven products being a plus.

• Perform ASIC power analysis and optimization at RTL and gate‑level (netlist)
• Drive PPA optimization using Synopsys Fusion Compiler
• Run and analyze reports from ASIC flows including Synthesis, Power, Timing, and Physical Design
• Develop scripts to post‑process log and report files for data extraction, formatting, and analysis
• Implement and review RTL blocks and UPF‑based power intent
• Analyze power trade‑offs across design and backend implementation
• Support power profiling at IP and SoC levels
• Document methodologies, results, and findings clearly and effectively
• Collaborate with cross‑functional teams to resolve power‑related issues

• 10+ years of experience as an ASIC Power Engineer, Physical Design Engineer, or CAD Engineer
• Strong experience with power estimation and analysis tools
• Hands‑on knowledge of low‑power design techniques and power trade‑offs
• Experience with RTL and netlist‑level power analysis
• Proficiency in Python, Tcl, and/or System Verilog scripting
• Familiarity with end‑to‑end ASIC flows (Synthesis, PD, Power, Timing)
• Bachelor s degree in Electrical Engineering, Computer Science, or equivalent experience

• Experience with Synopsys tools: DC, ICC, Fusion Compiler, Prime Power/PTPX, VCS, Verdi and/or Cadence Joules
• Knowledge of UPF power intent specifications
• Experience with silicon power characterization
• Exposure to IP/SoC‑level power profiling
• Strong skills in data analytics and visualization
• Experience using Excel and/or Matlab for data analysis and model fitting
• Background supporting AR/VR or Machine Learning silicon products