Signal Integrity Engineer, University Graduate, PhD, Platforms Infrastructure

Signal Integrity Engineer, University Graduate, PhD, Platforms Infrastructure

Google place Sunnyvale, CA, USA

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X This is a specialized role which requires physical interaction with hardware equipment in a simulated data center environment, utilizing Google labs, power, and safety equipment. Regular development and processing of engineering hardware must be performed on site.

• PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
• Experience in any signal integrity domain of electrical engineering through internships, academic research, or publications.
• Experience with Allegro, Matlab, and two or more of the simulation tools: HFSS, Clarity, ADS and Sigrity.

• Experience with Ser Des testing in a lab setting, and familiarity with Ethernet, PCIE, and DDR standards.
• Understanding of SERDES capabilities, and of FEC and its implications for system design.
• Understanding product development process for mass volume production design, with a focus on signal integrity and lab validation.
• Familiar with lab measurement tool (e.g., Vector Network Analyzer (VNA)).
• Understanding of PCB, connector, or cable design and assembly processes, including materials and component selection.

Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by custom hardware designed and made in-house. As a Hardware Engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concepts all the way through to high volume manufacturing.

Your work has the potential to shape the machinery that goes into our data centers affecting millions of Google users.

As a Signal Integrity Engineer, you will design and build the systems that are important to our largest and powerful computing infrastructure. You will see those systems from concepts all the way through to high volume manufacturing. You will support the machinery that goes into our data centers affecting millions of Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $126,000-$181,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Collaborate with electrical engineers, system engineers, design partners and vendors, to drive system SI design, explore layout and manufacturability tradeoffs, and ensure that product functions as required.
• Perform full-wave 3D Electromagnetic (EM) simulations for PCB critical transitions, including vias, connectors, and package-to-board interfaces to improve channel performance.
• Develop and validate system serial link models for pre-layout and post layout SI analysis.
• Manage system interconnect brings up and qualification, including configuring Ser Des (Serializer/Deserializer) settings to ensure adequate margin.
• Work with Ser Des Physical IP, package, board, connector, and cable vendors to develop new interconnect technologies.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories…