Sr. Chip Physical Design Engineer; Silicon Engineering

Sr. Full Chip Physical Design Engineer (Silicon Engineering)

Sunnyvale, CA

Space

X was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today Space

X is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

At Space

X we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together.

We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑in‑class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable.

Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

• Perform SOC top level physical design; floor‑planning, I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, partition hardening, chip level clock, feed through, special interface, and interconnect planning, bus routing, sequential pipeline planning and top level design for testability (DFT) planning
• Collaborate with chip architects, ASIC engineers, package engineers and block level physical design engineers to drive chip floorplan reviews and identify area, interconnect, IP integration, and floorplan improvement opportunities
• Perform chip timing budgeting and constraint pushdown to partition owners
• Work with static timing analysis, physical verification, electromigration/voltage drop, noise and other signoff teams to achieve closure and tapeout on time
• Run physical verification at chip level and provide feedback and guidance to block level physical design engineers to fix design rule check/layout versus schematic/antenna/electrical rule check/design for manufacturing violations
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience in industry

• Experience and deep understanding of SOC top level physical design flows (floor‑planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feed through flows, special interface/interconnect planning and implementation)
• Experience in IP integration (e.g. memories, I/O’s, analog IPs, Ser Des, DDR etc.)
• In-depth knowledge of industry standard EDA tools, understand their capabilities and underlying algorithms
• Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHz
• Strong knowledge of deep sub‑micron FinFET technology nodes (7nm and below) design problems and solutions (leakage power, signal integrity, etc.) multi‑corner and multimode timing closure, process variations, physical verification methodology and tapeout
• Familiar with implementation or integration of design blocks using Verilog/System Verilog
• Experience with clock domain crossings, DFT/Scan/MBIST/LBIST/JTAG/Boundary‑scan testing and understanding impacts on physical design flow
• Experience with…