ASIC Design Engineer
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-01-12
Listing for:
Intelliswift - An LTTS Company
Contract
position Listed on 2026-01-12
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
Intelliswift - An LTTS Company provided pay range
This range is provided by Intelliswift - An LTTS Company. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range$100.00/hr - $115.00/hr
Direct message the job poster from Intelliswift - An LTTS Company
Assistant Manager - Technical Recruitment | Strategic Sourcing, Technology HiringType: 12 Months contract to start with possible extension
Responsibilities- Lead micro‑architecture exploration and development of complex ASIC blocks and subsystems targeting data‑center applications including ML, network acceleration, and video transcoding.
- Design and implement RTL using Verilog, System Verilog, or HLS; responsible for linting, CDC, synthesis, timing closure, power optimization, and formal methods.
- Identify, integrate, and verify soft and hard IP components; work collaboratively with verification and emulation teams on test‑plan development, debug, and achieving design closure.
- Partner with physical implementation teams to meet timing, power, and area targets; aid in timing‑driven architecture trade‑offs.
- Collaborate cross‑functionally with verification, emulation, implementation, and post‑silicon validation teams to ensure first‑pass silicon success.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (or equivalent experience).
- 8+ years of hands‑on experience in micro‑architecture and RTL development for complex control/data‑path IP or SoCs.
- Proficient in Verilog/System Verilog/HLS, lint, CDC, synthesis flows, timing closure, power optimization, and formal verification methodology.
- Experience with RTL integration of subsystems such as CPU, NoC, memory, peripheral, or video‑codec.
- Strong scripting capabilities (TCL, Python, Perl, or Shell) for automation and design flows.
- Advanced degree (Master’s or PhD) in EE, CE, CS, or equivalent technical field.
- Proven track record of leading full chip ASIC projects from architecture to tape‑out.
- Prior involvement in data‑path intensive blocks (e.g., CPU, ML, network, or video processing).
- Familiarity with synthesis tools, timing closure, and formal verification methodologies.
Mid‑Senior level
Employment typeTemporary
Job functionSemiconductor Manufacturing, Computer Hardware Manufacturing, and IT Services and IT Consulting
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