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ASIC Power Engineer V

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: EPITEC
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Electrical Engineering, Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 110 - 120 USD Hourly USD 110.00 120.00 HOUR
Job Description & How to Apply Below
Job Title:

ASIC Power Engineer

Location:

Sunnyvale, CA

Job Type: Contract (6 month with possible extension)

Expected hours per week: 40 hours per week

Schedule:

Monday-Friday, Hybrid

Pay Range: $110.00 -$120.00 per hour with optional benefits including insurance (medical, vison, dental), PTO, 401(k) matching, etc.

Summary

ASIC Power Engineer to perform power analysis and optimizations in ASIC for Metas AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, tcl and System Verilog.

Responsibilities

• Perform PPA optimization with Fusion compiler.

• Perform RTL and netlist level Power analysis

• Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction

• Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)

• Implement some blocks at RTL and UPF

• Ability to document and communicate clearly

Minimum Qualifications

• 10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer

• Experience with power estimation tools and synthesis, some physical design

• Knowledge of power trade-offs in design and back end implementation

• Hands‑on experience in scripting, data analysis

• BS in Electrical Engineering/Computer Science or equivalent experience

Preferred Qualifications

• Synopsys (DC, ICC, PTPX/Prime Power, VCS, Verdi) and/or Cadence (Joules)

• Python, Perl (or similar) scripting and data-post-processing tools

• Excel (or Matlab) for model fitting, data visualization and analysis

• Experience in low power design, tools and methodologies including power intent UPF specifications

• Silicon Power Characterization

Must Have Skills

• Experience with Synopsys (DC, ICC, PTPX/Prime Power, VCS, Verdi) and/or Cadence (Joules)

• Should know how to use Python, Perl (or similar) scripting and data-post-processing tools

• Experience in low power design, tools and methodologies including power intent UPF specifications

• Silicon Power Characterizationli>

Nice to Have Skills

• Some power profiling experience at IP/SoC level

• Experience with Silicon Power Characterization

• Experience with Data analytics and visualization

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