SoC Silicon -Level Floorplan Engineer

Google place Sunnyvale, CA, USA

Apply

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in physical design (e.g., with a focus on floor planning, integration, or top-level chip assembly).
• Experience in physical design working on advanced nodes.
• Experience collaborating with cross-functional teams (e.g., architecture, RTL design, synthesis, verification).
• 3D IC design experience (e.g., multi-die partitioning, TSV planning, advanced chiplet and packaging technologies, optimizing PPA, and physical verification in a System-in-Package context).

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in scripting languages (e.g., Python, Tcl or Perl) and industry standard top-level tools including Innovus, Fusion Compiler.
• Experience working on various technologies (e.g., embedded processors, DDR,Ser Des, HBM, networking-on-chip fabrics, etc.).
• Experience using specialized EDA tools to resolve DRC/LVS/EMIR issues for leading edge nodes.
• Experience with SoC design methodologies for full chip power grid, global clocking, data path implementation, 3
  
  PIP integration, and bump planning.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be creating the initial physical layout of a chip top-level, defining block sizing/placement, power grids, and clock distribution to meet performance, power, and area (PPA) goals, requiring deep collaboration with architecture, RTL, and synthesis teams, using industry and internal tools, and driving early timing/congestion closure for complex modern SoCs. You will utilize full-chip planning and IP integration, delivering floorplan collaterals and collaborating for signoff.

This is a highly cross-functional and central role that will require interactions with numerous development teams.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

• Own the planning, creation, and delivery of top-level floorplan deliverables and implementation for Silicon SOC…