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SOC Engineering, Physical Design Architect

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: Synopsys, Inc.
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below
Position: SOC Engineering, Physical Design Architect- 13350

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced IC physical design expert, with strong leadership in digital implementation and signoff for complex, high-speed mixed-signal subsystems. You thrive in collaborative environments, can manage both local and remote teams, and have a proven track record of driving projects to tapeout. You’re hands‑on, detail-oriented, and passionate about optimizing performance, power, and area. Your communication skills and technical insight make you a go‑to resource for cross‑functional teams.

What You’ll Be Doing:
  • Lead and manage physical design teams for high-speed subsystem implementations.
  • Guide timing constraints and signoff for designs with hundreds of clocks.
  • Drive PNR flow for deep sub‑micron, multi‑million gate designs.
  • Execute synthesis, floor planning, partitioning, DFT, low power/UPF, and signoff tasks.
  • Collaborate with front‑end, analog, and program management teams.
  • Provide feedback for architectural and timing improvements.
The Impact

You Will Have:

  • Deliver signoff‑quality, high‑performance silicon solutions.
  • Mentor and develop engineering teams.
  • Drive process improvements and technical innovation.
  • Enhance Synopsys’ leadership in high‑speed IP.
  • Facilitate successful cross‑team collaboration.
  • Enable next‑generation chip architectures.
What You’ll Need:
  • MS in Electrical Engineering; 10+ years in physical design.
  • Hands‑on RTL‑GDSII implementation and tapeout experience.
  • Team leadership (local and remote).
  • Expertise in Synopsys tools and flows.
  • Strong scripting and software skills.
Who You Are:
  • Inclusive leader and effective communicator.
  • Innovative, collaborative, and quality‑driven.
  • Thrives in dynamic environments.
The Team You’ll Be A Part Of:

Join a global engineering team advancing high‑speed silicon IP design. We value innovation, inclusion, and technical excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.

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