Synthesis & STA Engineer

Team Introduction

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape‑out, mass production, packaging, testing, and board‑level verification.

They collaborate closely with front‑end chip teams across business units to drive R&D progress and mass production deployment for chip.

• Perform logic synthesis and design optimization for architectures and RTLs.
• Timing constraints (SDC) preparation and tuning, and conduct hierarchical/full‑chip STA signoff and timing closure.
• Implement low‑power design techniques and constraints (UPF, clock gating, power gating, dynamic voltage scaling).
• Formal verification & equivalence checking using formal verification tools (Conformal, Formality).
• Work with front‑end engineers for architectural exploration and planning.
• Work with backend engineers on floor planning, place & route (P&R), congestion analysis, and timing bottlenecks.

• Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field.
• 3+ years of experience in IC design with a focus on sdc, synthesis, timing signoff, low‑power implementation, and power optimization.
• Proficiency in Verilog/System Verilog, RTL‑to‑GDSII flow, and EDA tools (Fusion Compiler, Genus/Innovus+, Prime Time/Tempus, Formality, Conformal LP).

• Strong understanding of timing analysis, multi‑clock domain handling.
• Familiarity with DFT methodologies (scan, bscan, mbist) and understanding of DFT related timing analysis is preferred.