Digital Design Engineer

Build next-gen FPGA systems that power global connectivity. We're hiring a Senior Digital Design Engineer to design high-speed, low-power signal processing hardware.

This Jobot Job is hosted by:
Tarek Hamzeh
Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.
Salary: $150,000 - $180,000 per year

A bit about us:

We’re seeking a Senior Digital Design Engineer to lead the architecture and implementation of advanced FPGA-based systems for real-time signal processing and communication applications. You’ll work on high-performance, low-power designs that enable next-generation connectivity across a global network of devices.

In this role, you’ll collaborate with cross-functional teams of hardware, software, and systems engineers to design, validate, and optimize FPGA modules responsible for localization, decoding, and data transfer. Your contributions will directly influence system performance, scalability, and reliability in a rapidly evolving environment.

Why join us?

Salary: $150K – $180K (based on experience)
Comprehensive Benefits:
Health, Dental, Vision, HSA options
Unlimited PTO and flexible time off
Paid Parental Leave
Learning & Development Stipend
Wellness Support:
Monthly health & fitness allowance
Sabbatical Program:
Recharge and explore new ideas after five years
Cutting-Edge Hardware:
Work on advanced digital and space-based communication systems
Additional Perks:
Team offsites, company swag, and more

Job Details

Key Responsibilities

Design, develop, and verify RTL code (Verilog/System Verilog) for real-time digital signal processing systems.
Implement packet decoders and communication protocol logic (e.g., Bluetooth® Low Energy, Zig Bee, LoRa, or custom PHYs).
Integrate high-speed memory interfaces (DDR/DDR3/DDR4) and serial interfaces (LVDS, SPI, I2C, UART, JESD
204, PCIe, Ethernet).
Perform synthesis, timing closure, and resource optimization on FPGA platforms (Xilinx or Intel/Altera).
Collaborate with RF, firmware, and systems engineers to optimize end-to-end communication performance.
Conduct system-level analysis and simulation to ensure signal integrity, throughput, and latency targets are met.
Develop test benches, verification suites, and automation scripts (Python, Tcl).
Drive system-level reviews and contribute to architecture decisions across hardware and embedded systems.

Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in FPGA design and real-time signal processing.
Proficiency in Verilog/System Verilog, digital communication systems, and DSP fundamentals (filtering, correlation, fixed-point arithmetic).

Experience with high-speed memory and serial communication interfaces.
Strong background in FPGA synthesis, simulation, and performance optimization.
Familiarity with simulation and verification tools (Model Sim, Questa, Vivado, VUnit).
Skilled in scripting and automation (Python, Tcl).
Ability to work independently in a fast-paced, collaborative engineering environment.
Excellent communication and cross-functional collaboration skills.

Preferred Experience

Designing distributed DSP systems across multiple FPGAs or compute nodes.
Integration of soft-core or hard-core processors (ARM, RISC-V) and embedded Linux environments (e.g., Peta Linux).

Experience with synchronization techniques (preamble detection, timing recovery, frequency offset correction).
Familiarity with lab instrumentation for validation and debugging (oscilloscopes, logic analyzers, RF tools).
Knowledge of low-power digital design and space-grade reliability techniques.
Understanding of short-range RF communication standards such as Bluetooth® Low Energy.

Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.

Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal,…