Packet Processor Architect

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference.

We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro‑LED company).

The company is in execution mode and has a world-class engineering team with decades of experience in state‑of‑the‑art silicon, packaging, optics, software, and systems. Eridu is working with best‑in‑class supply chain partners including silicon, packaging and systems.

We are looking for a highly experienced Packet Processor Architect to lead the definition and implementation of Eridu's industry leading Networking ASIC. This is a unique opportunity to help shape the future of AI Networking.

• Define and architect packet processing pipelines including related lookup tables and metadata structures for high-performance networking ASICs, including ingress/egress processing, switching/bridging and routing, hash tables and memory lookups, classification, ACL, various tunneling protocols like VxLAN, GRE, IPinIP, QoS, scheduling, traffic management, and congestion control.
• Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications.
• Collaborate with the chip and system microarchitects to align the packet processor architecture with system-level goals for throughput, latency, programmability, and power efficiency.
• Lead modeling and feasibility analysis of packet flow behavior across L2/L3/L4 layers to validate architectural choices, including throughput, latency, power and area efficiencies.
• Drive architectural decisions involving classification, table and lookup optimizations, resource allocation and scalability.
• Work closely with RTL, Verification, Firmware, and Physical Design teams to ensure seamless design implementation and handoff.
• Guide integration of internal and external IPs (e.g., TCAM, MAC, PCIe, Ser Des, DMA) into the broader packet architecture.
• Participate in design reviews, performance modeling, Test and Verification strategies and architectural trade‑off analysis. Provide support for various networking protocols and standards related to packet processing.
• Contribute to post‑silicon validation and tuning of packet flows for performance and correctness. Investigate and resolve complex issues related to packet processing, working closely with cross‑functional teams including hardware engineers, firmware developers, and system architects.
• Define architecture-level development methodologies and influence cross‑functional design best practices.

• MSEE or equivalent with 15+ years of experience in networking or data‑path ASIC architecture and design.
• Proven success in architecting packet‑processing engines in high‑throughput ASICs or SoCs. Experience in designing hash functions, hash tables and lookup engine optimizations.
• Deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications.
• Familiarity with programmable pipelines, parser/deparser logic, and hardware scheduling engines.
• Demonstrated expertise in microarchitecture definition, performance modeling, and trade‑off analysis.
• Solid experience…