Senior Engineer, DFT

Overview

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes.

This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

We are seeking a Senior DFT Engineer with 5+ years of hands-on implementation experience across MBIST, BISR, Boundary Scan, and IJTAG
. This is a highly execution-driven role requiring end-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug
.

In this role, you will partner closely with RTL, Physical Design, and ATE teams to deliver clean DFT signoff and robust test coverage for complex SoC designs

• Perform hands-on DFT implementation
  , including:
• MBIST and BISR insertion and integration
• Boundary Scan (IEEE 1149.x) insertion
• IJTAG (IEEE 1687) insertion and connectivity
• Execute DFT verification, debug, and DFT DRC closure using Siemens Tessent
• Identify, debug, and resolve DFT rule violations at both block and top levels
• Run, analyze, and debug Spy Glass DFT/RTL checks
  , working with design teams to close violations
• Generate, simulate, and debug MBIST and logic ATPG patterns
• Analyze test results and drive test coverage improvement and closure
• Develop and validate DFT timing constraints for scan, BIST, and test modes
• Create and maintain TCL scripts to automate DFT insertion, verification, and analysis flows
• Support hierarchical DFT implementation and resolve integration issues
• Collaborate with RTL and Physical Design teams to address DFT-related design issues
• Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up and debug
• Assist with ATE pattern conversion and debug as needed

• Bachelor’s degree with 6+ years of relevant experience, or Master’s degree with 5+ years of relevant experience
• 5+ years of hands-on DFT implementation experience
• Strong proficiency with Siemens Tessent
  , including:
• MBIST / BISR insertion and verification
• Boundary Scan (IEEE 1149.x)
• IJTAG (IEEE 1687)
• ATPG pattern generation and coverage analysis
• Proven ability to resolve DFT DRCs, connectivity issues, and testability problems
• Strong TCL scripting skills for DFT automation and flow execution
• Experience developing and validating scan and test-mode timing constraints
• End-to-end DFT lifecycle experience
  , from RTL/netlist through silicon debug
• Strong debugging skills
  , attention to detail, and sense of ownership
• Excellent verbal and written communication skills

• Experience driving MBIST coverage improvement and repair efficiency optimization
• Pattern bring-up and debug
• Tester pattern conversion
• Exposure to mixed-signal or SERDES DFT
  , such as IOBIST or…