ASIC Clocks Verification Engineer — Hybrid & Equity

A leading technology company is seeking a Clocks Verification Engineer to collaborate with architects and ASIC designers on GPU clock design. Ideal candidates will have a Master's degree in Electrical Engineering and practical experience with System Verilog and UVM. Responsibilities include designing high-frequency clock structures and debugging silicon bugs. Competitive base salary ranges from 116,000 to 189,750 USD based on level and experience, with eligibility for equity and benefits.

Applications accepted at least until February 24, 2026.
#J-18808-Ljbffr