Field-Programmable Gate Arrays Engineer

Pay Rate: up to $60/hr on w2 (No C2C or 3rd parties)

Location:
Onsite in Santa Clara, CA

Schedule: Mon‑Fri 8:00 AM PST – 4:00 PM PST

This role focuses on designing, developing, and supporting FPGA‑based solutions for advanced robotic and medical systems. The engineer will own RTL design from architecture through validation, working hands‑on across the full FPGA development lifecycle, including simulation, timing closure, hardware bring‑up, and system‑level debugging. The position requires close collaboration with hardware, firmware, software, and systems teams in a highly cross‑functional, regulated R&D environment to deliver reliable, safety‑critical technology.

Key responsibilities include, but are not limited to:

• Designing, developing, optimizing, and maintaining FPGA RTL using Verilog/System Verilog and/or VHDL
• Supporting the full FPGA development lifecycle, including synthesis, place‑and‑route, timing closure, and bitstream generation
• Performing functional simulation, verification, and system‑level debugging
• Supporting board bring‑up, testing, integration, and validation
• Collaborating closely with hardware, firmware, software, and systems engineering teams
• Documenting design decisions, test results, and process improvements
• Participating in design reviews and regulated development activities

Required

Skills and Experience:

• 4+ years of hands‑on FPGA design and development experience
• Strong understanding of digital logic, timing analysis, and debugging
• Proficiency in Verilog/System Verilog
• Experience with FPGA tool chains such as Xilinx Vivado, Lattice Diamond, or equivalent
• Bachelor’s degree in Mechanical Engineering, Electrical Engineering, or a related scientific field
• Strong collaboration and communication skill.

Preferred

Skills and Experience:

• Prior experience in medical devices, robotics, or safety‑critical systems
• Exposure to regulated environments such as FDA, IEC, or ISO
• End‑to‑end FPGA ownership from architecture through validation
• Experience debugging real hardware issues beyond simulation
• Familiarity with high‑speed protocols such as PCIe, Ethernet, DDR, or Aurora
• Experience using simulation, verification, and hardware debug tools (logic analyzers, oscilloscopes)
• Cross‑functional collaboration with mechanical, systems, or clinical teams