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DDR Memory Controller Design Engineer; GHz+ ASIC

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Qualcomm
Full Time position
Listed on 2026-02-06
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 107400 - 161200 USD Yearly USD 107400.00 161200.00 YEAR
Job Description & How to Apply Below
Position: DDR Memory Controller Design Engineer (1GHz+ ASIC)
A leading technology innovator is seeking ASIC Design Engineers to develop next-generation high-speed DDR Controllers. This role involves working on architecture, design, and deployment of Memory Controllers for LPDDR/PCDDR technologies. Candidates should have experience with DDR controller architectures and a bachelor's degree in a related field. The pay range is $ - $, complemented by a competitive benefits package and potential bonuses.
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