Senior ASIC Physical Design Engineer, Netlisting

Senior ASIC Physical Design Engineer, Netlisting

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that only we can pursue, and that matter to the world.

We are looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team.

• Drive physical design of high‑frequency, low‑power CPUs, GPUs, SoCs at block, cluster, or full‑chip level, focusing on netlist‑related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks, MTBF analysis, logic synthesis, and netlist quality checks.
• Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.
• Expertise in logic equivalence checking/FV from RTL to tapeout with industry‑standard tools, deep understanding of hardware architecture, and hands‑on skills in RTL/logic design for timing closure.
• Experience in clock‑domain‑crossing checking, MTBF analysis, either with industry‑standard tools or in‑house tools.
• Background with logic synthesis at either block or full‑chip level, project execution and/or flow development.
• Strong experience in full‑chip/sub‑chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
• Expertise and in‑depth knowledge of industry‑standard EDA tools related to the field.
• Proficiency in programming and scripting languages such as Perl, TCL, Make, Python, etc.

• Experience in logic synthesis and equivalence checking/FV with familiarity to industry tools and flow.
• Strong hands‑on debugging capability and problem‑solving skills.
• Background in DFT timing closure for various modes such as scan shift and capture, transition faults, BIST, etc.
• Demonstrated experience or strong drive to improve workflows and productivity through effective AI utilization.

Base salary determined by location, experience, and comparable positions; base salary range is $136,000–$212,750 for Level 3 and $168,000–$264,500 for Level 4. You also may be eligible for equity and other benefits.

Equity, comprehensive health benefits, retirement plans, and other perks typical of NVIDIA.

Applications for this job will be accepted at least until January 11, 2026. NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.

Location:

Santa Clara, CA.