Advanced Packaging Modeling Expert - FEA

Advanced Packaging Modeling Expert - FEA page is loaded## Advanced Packaging Modeling Expert - FEAlocations:
Santa Clara,CAtime type:
Full time posted on:
Posted Todayjob requisition :
R2517933
** Who We Are
** Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT.

If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.
** What We Offer
** Salary:$ - $

Location:

Santa Clara,CAYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more.

At Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our .
* ** About the Role
** We are looking for an expert, highly experienced Senior FEA Engineer to join our Advanced Packaging Modeling team in Santa Clara, CA. This is a critical role focused on developing thermal-mechanical simulations to support the design, development, and qualification of next-generation semiconductor packaging technologies. You will play a key role in shaping the future of advanced packaging by providing simulation-driven insights that influence architecture, materials, and process decisions.  

This position offers the opportunity to work at the forefront of semiconductor innovation, collaborating with engineers and researchers across multiple business units including design, process integration, reliability, and manufacturing.  
** Key Responsibilities**  + Develop and validate detailed finite element analysis (FEA) models to simulate thermal and mechanical behavior of advanced semiconductor packages.  + Perform simulations to evaluate stress, strain, warpage, delamination, thermal cycling, and reliability risks across a wide range of package architectures (e.g., flip-chip, fan-out, 2.5D/3D IC, chiplet-based designs, TSVs).  + Conduct thermal modeling to assess heat dissipation in complex package structures, supporting thermal design optimization and advanced cooling technology development.  

+ Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations.  + Support technology roadmap development by evaluating new materials, interconnect structures, and process flows from a thermo-mechanical reliability perspective.  + Drive design-of-experiment (DOE) studies and sensitivity analyses to understand key drivers of package performance and reliability.  + Contribute to the development and automation of internal simulation workflows, tools, and best practices to improve modeling efficiency and accuracy.  

+ Document and present simulation methodologies, results, and recommendations to both technical and executive audiences.  + Stay current with industry trends, emerging technologies, and academic research in advanced packaging and simulation methodologies.
* ** Required Qualifications**  + M.S. or Ph.D. in Mechanical Engineering, Materials Science, Applied Physics, or a related field.  + 5 years of hands-on industry experience in thermal-mechanical FEA modeling, in the semiconductor or electronics packaging domain.  + Thorough understanding of advanced packaging technologies, including flip-chip, fan-out wafer-level packaging (FOWLP), 2.5D/3D integration, chiplet architectures, and through-silicon vias (TSVs).  +…