Senior Signal and Power Integrity Engineer

Senior Signal and Power Integrity Engineer

We’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.

This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.

You will lead the Signal and Power Integrity (SI/PI) strategy for our next-generation, high-performance storage platforms, ensuring system-level electrical robustness. You will own the end-to-end electrical architecture—from high-level concept definition and advanced modeling to final lab validation and compliance sign-off. This critical role involves acting as a technical leader and cross-functional facilitator, collaborating with Hardware Design, PCB Layout, and firmware teams to ship robust, cutting-edge products globally.

• Architect and own the SI strategy for all cutting-edge, high-speed interfaces (e.g., PCIe Gen5+, 800G Ethernet, DDR5), ensuring product reliability and maximizing performance margins from initial link budgets through production release.
• Drive Power Integrity (PI) excellence by establishing and validating robust Power Delivery Network (PDN) targets, including impedance profiling, decoupling optimization, and mitigating SSN for complex, high-current draw hardware designs.
• Define and enforce global design standards by collaborating with PCB layout and mechanical teams on stackups, materials, routing rules, and constraints to achieve first-pass silicon success and manufacturing quality across product lines.
• Serve as the SI/PI technical lead for complex system-level debug, root-cause analysis, and corrective action implementation to resolve critical issues across prototypes, validation, and field escalations.
• Elevate engineering efficiency by developing and standardizing automated simulation flows, reporting pipelines (using Python or MATLAB), and Continuous Integration (CI) style checks for model and layout quality across the hardware organization.

• Expert-level proficiency in high-speed channel design and validation for modern interfaces like PCIe Gen4+, 25G+ Ser Des Ethernet, and DDR4/DDR5, including deep knowledge of EM theory, crosstalk mitigation, and jitter analysis.
• Mastery of industry-standard EDA tools (e.g., Sigrity, ADS, HFSS, Hyper Lynx) for pre- and post-layout SI/PI analysis (IBIS‑AMI, COM, and channel modeling) and hands-on lab validation using high-speed instruments (VNA, TDR, BERT, Oscilloscopes).
• Advanced Power Integrity design experience in target impedance methodology, VRM modeling, noise coupling analysis, and defining component placement strategies to mitigate SSN and ground bounce.
• Demonstrated ability to lead technical initiatives and drive complex cross-functional decisions, acting as a facilitator and mentor to junior engineers while documenting best practices to champion "quality by design."
• Fluency in developing scripts (e.g., Python, MATLAB) for automating SI/PI model extraction, simulation workflows, post-processing, and generating standardized reports.
• We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.

#LI-ONSITE

Salary ranges are determined based on role, level, and location. For positions open to candidates in multiple geographical locations, the base salary range is reflective of the labor market across the applicable locations.

This role may be eligible for incentive pay and/or equity.

There is no Final date to receive applications and we accept applications on an ongoing basis until the job is filled.

The annual base salary range is: $175,000 - $263,000 USD

• Pure Innovation
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