Senior Physical Verification Application Engineer

Senior Physical Verification Application Engineer

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Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting‑edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry‑leading technology, a rich IP portfolio, a world‑class design ecosystem, and an operationally resilient global manufacturing supply chain.

Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape‑outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.

• Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges
• Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution
• Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations

• Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
• Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape‑outs
• Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies

• Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)
• Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations
• Drive methodology improvements to streamline customer design workflows and enhance verification productivity

• Deliver customer‑facing technical support with focus on physical verification challenges and solutions
• Support customers through complex verification issues and advanced process technology adoption
• Ensure maximum customer satisfaction through expert guidance and responsive technical support

• Self‑driven and results‑oriented with capability to effectively manage multiple complex tasks
• Strong analytical problem‑solving skills for complex physical verification challenges
• Effective communication skills with experience in collaboration, active listening, and providing constructive feedback

• US citizenship required
• Ability to obtain a US Government Security Clearance
• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or a STEM related field of study
• 5+ years of experience with advanced CMOS processes (22nm and below)
• 4+ years of combined experience in layout verification and parasitic extraction EDA tools
• 4+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)

• Active US Government Security Clearance with a minimum of Secret level
• Postgraduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field of study
• Hands‑on experience in one or more areas (LVS, DRC, ERC, PERC)
• Experience in parasitic extraction tools, e.g., StarRC, Quantus, or xACT EDA tools
• Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
• Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
• Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work
• Customer‑facing experience

• Opportunity to work with cutting‑edge…