Principal Interconnect Micro-architect and RTL Design Engineer

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AMD is looking for an engineering leader passionate about driving the best Power, Performance, Area (PPA) of AMD’s SoC coherent Interconnects Data Fabrics IPs for next generation AMD AI devices. The ideal candidate will have proven experience in developing scalable complex digital IP microarchitectures to deliver industry leading performance/area and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team, and physical design team to drive the RTL design and microarchitecture of modular network on chip IPs for AMD Data Center silicon SoCs.

The candidate will drive new methodologies to build scalable, modular network on chips. You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AMD Data Center SoCs.

The ideal candidate has passion for modern, complex microarchitecture, and efficient digital design. Should have demonstrated experience in developing complex highly scalable, modular microarchitectures for SOC with focus on coherent and non-coherent switch fabric IP and must possess leadership and technical skills to influence and drive SOC methodologies to enable delivery of multiple highly complex, high quality, SoCs in shorter time.

Able to communicate effectively and work optimally with different teams across AMD.

• Technical Microarchitecture lead on AMD Data Fabric RTL design team focused on driving the best scalability, modularity, power, performance, and area
• Explore and dive initiatives to achieve best switch fabric scalability, modularity, and reuse across multiple advanced Data Center AI accellerator SOCs
• Develop technical relationship with broader AMD design community and peers
• Stay informed on latest trends on innovations on switch fabric hardware architecture and implementation.
• Close architecture, and micro-architecture requirements, drive technical specifications for Data Fabric IP to meet those requirements, and drive RTL execution
• Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop RTL and microarchitecture solutions to achieve requirements
• Knowledge sharing and other contributions to AMD Data Fabric architecture and design
• Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
• Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

• Experience with highly scalable, configurable switch fabrics (coherent and non-coherent)
• Experience with modern heterogenous systems including CPU, GPU, and AI accelerators.
• Experience with SOC and IP creation automation for different microarchitectures
• Proven track record of defining and delivering complex IP and SOC microarchitectures.
• Expert level ability in optimizing and performing tradeoff analysis across multiple domains including PPA, design, microarchitecture, and architecture, verification, and schedule.
• Expert of RTL design, Verilog and System Verilog
• Deep knowledge of front-end tools
• experience with synthesis, static timing, DFT
• Exposure to physical design and verification methods
• Experience with scripting languages such as Perl, Python, Unix shells and Makefiles, and…