Sr. DFT Engineer at Ambarella – Santa Clara,

• Sr. DFT Engineer at Ambarella – Santa Clara, United States

Ambarella, a worldwide leader in edge AI semiconductors and software, is on a mission to bring artificial intelligence to all types of everyday devices, for enhanced environmental perception in everything from security cameras to robots to autonomous vehicles.

Position Responsibilities:

• DFT implementation (Scan, Compression, MBIST, LBIST, and Streaming Scan Network) from RTL to Post-Production for complex multi-million gate Computer Vision SoC.
• Analyze clocking scheme and implement clock control structure for at-speed scan testing
• Develop/Generate high-quality scan and mbist patterns.
• DFT Verification (including post place-and-route timing simulations).
• Work with Product Engineering team to bring up scan & mbist patterns on ATE.
• Support silicon production activities including failure diagnosis and test optimization.
• MS in Electrical / Computer Engineering or BS in Electrical/Computer Engineering with 1-5 years of experience in DFT implementation
• Knowledge of DFT fundamentals
• Knowledge of Logic design and timing
• Knowledge of Verilog and Python
• Knowledge of Mentor Tessent tools is a plus
• Knowledge of scan diagnostics is a plus

The base salary range is $135,000– $196,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.