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ASIC Lead Physical Design Engineer

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Elastics.cloud, Inc.
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer, Manufacturing Engineer
Salary/Wage Range or Industry Benchmark: 175000 - 220000 USD Yearly USD 175000.00 220000.00 YEAR
Job Description & How to Apply Below

Key Responsibilities

  • Physical design engineer supporting the full chip creation, layout and final delivery of GDS-2.
  • Work with ASIC vendor to drive timing closure/STA, layout, RAS features and on‑chip repair methodology for the best solution in the chip industry.
  • Develop and own physical design implementation of multi‑hierarchy low‑power designs including physical‑aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
  • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
  • Deliver multiple ASICs with physical design of an end‑to‑end integration of ASIC/SoC design.
Job Requirements
  • Bachelor’s degree in Electrical Engineering or equivalent similar experience.
  • 10+ years’ experience in physical design.
  • Understanding of RTL2

    GDSII flow and design tapeouts in 7nm or below process technologies.
  • Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
  • Experience working with EDA tools such as DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, or Calibre.
  • Experience running physical‑aware logic synthesis and achieving optimal synthesis QoR on low‑power designs.
  • Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
  • Experience in block‑level and full‑chip floor‑planning and power grid planning.
  • Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
  • Experience with Python, TCL, Perl programming.
  • Multiple ASICs taking from inception to final delivery.
  • Multiple ASICs delivered in production.

The expected base salary range for this full‑time position is $175,000 to $220,000. The base salary offered will be based on a candidate’s relevant experience to the job role, location, education, experience level, and skill set. In addition to base salary, we offer 401K, Unlimited PTO, Health insurance, and Stock Options.

Elastics.cloud is an equal‑opportunity employer, committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Elastics.cloud will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment.

Please get in touch with us to request an accommodation.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Engineering and Information Technology

Industries

Semiconductor Manufacturing

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