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Lead PLL Analog Design Engineer; FinFET

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: AMD
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Electrical Engineering, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below
Position: Lead PLL Analog Design Engineer (FinFET)
A leading semiconductor company in Santa Clara is seeking an experienced Circuit Design Engineer. The role involves designing complex PLL circuits, mentoring junior engineers, and ensuring compliance with verification flows. Candidates should have expertise in mixed signal circuit design, proficiency with Cadence tools, and strong analytical skills. This position is ideal for those with a Master's in electrical engineering and a solid understanding of transistor-level design.

Visa sponsorship is not available for this role.
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