Senior Design Verification Engineer

Global Technical Recruiter | Power Electronics, Semiconductors, AI & Software | US, UK & Europe | Engineering, Leadership & Commercial Roles

Type: Contract (12+ months)

Start: ASAP (flexible)

A high-performing SoC verification specialist is needed for a fast-moving Bay Area hardware team building next-generation, high-performance silicon. You’ll take ownership of verification for complex I/O and interconnect subsystems, partnering closely with design, architecture, and international verification teams to deliver high-confidence sign-off.

This is a hands‑on role for someone who enjoys building clean, scalable verification environments and solving tough debug problems at the boundary of RTL, protocols, and system behavior.

• Own verification for complex, multi‑IP subsystems (I/O, interconnect, networking/packet flows depending on project scope).
• Define verification strategy, plans, and sign-off criteria aligned to architecture requirements.
• Build and maintain robust UVM verification environments using System Verilog.
• Create high‑quality constrained‑random tests, checkers, scoreboards, and coverage models.
• Drive protocol‑level verification and debug, with a strong emphasis on PCIe behavior and corner cases.
• Debug issues across simulation, waveforms, RTL, and (where relevant) firmware/software interactions.
• Collaborate with distributed teams (including India and potentially East Asia), supporting reviews and execution.

• 8+ years hands‑on Design Verification / Verification experience in semiconductor, networking, compute, or accelerator‑class hardware.
• Strong System Verilog and UVM expertise (including building/owning UVM environments).
• Proven PCIe verification experience (Gen4/5/6 exposure is a plus, but PCIe depth is required).
• Solid background in constrained‑random verification and coverage‑driven methodologies.
• Ability to independently drive tasks, communicate clearly, and deliver to sign‑off quality.
• SVA (System Verilog Assertions) and assertion‑based verification.
• Experience with one or more of: UCIe / die‑to‑die interfaces / chiplet‑based systems, CXL‑class fabrics / UALink or similar high‑speed interconnects, Ethernet/networking protocols, Packet‑processing architectures or networking datapaths.
• Experience verifying large‑scale subsystems with multiple interacting IPs.
• Track record working with international teams in a lead or mentoring capacity.
• Familiarity with common DV tool chains (e.g., VCS/Xcelium/Questa, Verdi/DVE, regression automation).

• A technically serious environment with real ownership and autonomy.
• Complex, protocol‑heavy verification challenges (not just test execution).
• Collaborative team culture with a strong focus on quality and delivery.

We are actively submitting candidates for this role. Reach out to Jaimie Javier at PER International on Linked In or email your CV to to apply or learn more.

Mid‑Senior level

Contract

Appliances, Electrical, and Electronics Manufacturing and Semiconductor Manufacturing