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Systems Engineer Electronics Engineer

Senior UVM Verification Engineer – SystemVerilog

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Celestial AI
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 200000 USD Yearly USD 150000.00 200000.00 YEAR
Job Description & How to Apply Below
A high-tech startup in California is seeking an experienced Verification Engineer proficient in System Verilog and UVM methodologies. The role involves developing robust verification strategies and enhancing the team's verification infrastructure. Candidates should have a Bachelor’s degree in electrical engineering and at least 5 years of relevant experience. The position offers a competitive salary of $–$, alongside attractive benefits and an opportunity to work with dedicated professionals in a collaborative environment.
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Position Requirements
10+ Years work experience
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