Silicon Design Package Engineer - Tech M
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-01-12
Listing for:
Saransh Inc
Full Time
position Listed on 2026-01-12
Job specializations:
-
Engineering
Electronics Engineer, Electrical Engineering, Systems Engineer, Hardware Engineer
Job Description & How to Apply Below
Silicon Design Package Engineer - Tech M
Role:
Silicon Design Package Engineer
Location:
Santa Clara, CA
This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies.
Tools & KnowledgeMentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).
Technical Expertise- Multi-layer package design experience.
- Understanding of substrate manufacturing Design Rules and Assembly Rules.
- Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
- Flip-chip package design concepts.
Mid-Senior level
Employment typeContract
Job functionDesign, Art/Creative, and Information Technology
IndustriesIT Services and IT Consulting
#J-18808-LjbffrTo View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×