Senior Signal Integrity​/Power Integrity; SI​/PI Engineer

Senior Signal Integrity / Power Integrity (SI/PI) Engineer

Full-time

Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges.

At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation.

Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do.

Arista’s cutting-edge Ethernet and optical networking platforms are built to push the limits of performance, density, and power efficiency. This wouldn’t be possible without our Signal Integrity (SI) and Power Integrity (PI) engineers who design, simulate, and characterize interconnects enabling the fastest Ser Des technologies in the industry. We’re looking for a Senior Signal Integrity / Power Integrity Hardware Engineer to join our Hardware Design team at our headquarters in Santa Clara, CA.

In this role, you’ll work at the intersection of advanced simulation, next-generation Ser Des (112G/224G/448G PAM4), and innovative routing, packaging, and power delivery techniques. Your work will directly influence the architecture and layout of Arista’s next-generation Ethernet and optical systems for hyperscale, AI, and cloud networking.

• Lead SI and PI efforts for high-speed electrical and optical interconnects across Arista’s Ethernet platforms, optical transceiver modules, and high-density optical engines.
• Perform 3D EM design and simulation of high-speed interconnects (channels, vias, packages, and connectors) for 112G/224G/448G PAM4 Ser Des using tools such as Ansys HFSS, SiWave, Keysight ADS, Cadence Sigrity, CST, and SiSoft QSI.
• Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.
• Conduct S-parameter and time-domain measurements (VNA, TDR, BERT, eye diagram, jitter, BER) to extract channel performance and validate modeling correlation.
• Perform link-level analysis for advanced standards (Ethernet 800G/1.6T, PCIe Gen6/Gen7, CXL) using tools such as Keysight ADS or Cadence System
  
  SI.
• Design and optimize PCB stackups, via structures, breakout regions, and connector transitions to meet compliance with IEEE, CEI, and MSA standards.
• Work closely with hardware, mechanical, optical, ASIC, and packaging teams to optimize stack-up, breakout, and routing strategies for high-density designs and ensure manufacturability and reliability.
• Define routing constraints, reference plane designs, and return path continuity for minimal signal degradation.
• Design and optimize PDNs to meet target impedance, minimize noise coupling, and support fast transient loads for high-speed DSPs and ICs.
• Provide SI/PI layout guidelines to PCB designers and review placement/routing for high-speed paths and power domains.
• Research and prototype novel materials, backplane concepts, and low-loss interconnect topologies to meet next-generation performance targets.
• Support bring-up and debug of production boards, working cross-functionally to root-cause SI/PI-related issues.
• Engage with ASIC, connector, and packaging vendors to support co-design and channel optimization across multiple integration layers.
• Drive root cause analysis of SI/PI-related issues during validation and production builds.

• B.S. or higher in Electrical Engineering, Applied Physics, or a related field with emphasis on…