Server RAS Architect

Company

Qualcomm Technologies, Inc.

Engineering Group, CPU Engineering

Hiring in Multiple locations:
Austin;
Portland;
Santa Clara

Qualcomm Data Center team is developing high performance, energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work!

We are dedicated to transforming industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you’ll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing server-class high performance solutions that are highly optimized for the needs of the server product.

We are seeking a highly experienced RAS (Reliability, Availability, Serviceability) architect to join our team. If you possess a deep understanding of CPU system design and have a passion for architecting and designing complex, high performance and low power designs at advanced process nodes, we would be pleased to hear from you. This critical role involves architecture of the complete RAS and error handling solutions for CPU server by collaborating with other CPU and SoC architects.

The ideal candidate will have extensive knowledge of CPU and SoC architecture for datacenter SoCs, including experience in microarchitecture and design of coherent CPU subsystems. CPU subsystem microarchitecture involves design and deployment of data, control and debug features using interconnects, power management, RAS, and debug and trace blocks. Strong analytical, problem-solving, and communication skills are essential for excelling in this position.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

• Master’s in Computer Science/Engineering, Electrical Engineering, or related field.
• Over 7 years of experience in architecting RAS solutions for complex server SoCs.
• In-depth understanding of the interaction of on-chip errors and error handling flows with system firmware/software.
• Detailed knowledge of multiprocessor system architecture, memory and input-output subsystems, high-speed interconnects, operating systems/hypervisors, platform firmware, Error correcting codes (ECC).
• Strong expertise in power management of a high-performance system including management of active power, idle low power and silicon/system limits.
• Strong expertise in defining and developing debug features associated with high performance designs.
• Strong technical documentation skills, along with excellent written and verbal communication abilities.
• 15+ years in developing RAS architecture for CPUs and/or SoCs.
• Experience with ARM ISA and related RAS specifications.
• Expertise in quantifying FIT rates of functional blocks, SoCs and the platform.
• Expertise in silicon and system test methodologies to quantify benefits of RAS mechanisms.
• Experience in micro-architecture and/or design of RAS solution for multiple functional blocks of a CPU/SoC like L2/L3, directory, interconnects, memory controllers, etc.
• Understanding of advanced features like Chipkill, forward error correction.
• Strong understanding of DFx technologies like DFT, DFY, DFM.

• Work with chip architect to understand architecture concept and high level requirements.
• Define and document RAS and Error Handling strategy for the chip.
• Collaborate with other stakeholders to quantify…