Senior FPGA Compiler Software Engineer

Senior Staff FPGA Compiler Software Engineer

Join to apply for the Senior Staff FPGA Compiler Software Engineer role at Altera.

Become a member of our world‑class software research and development team. Altera® develops innovative programmable logic technologies that are easy to use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end‑to‑end broad portfolio of products, including FPGAs, CPLDs, IP, development tools, system on modules, Smart

NICs and IPU, provides the flexibility to accelerate innovation for many customers worldwide.

• Leading research and development efforts to explore novel optimization algorithms for our FPGA CAD software tools, including global and detailed routing as well as state‑of‑the‑art retiming for our Hyperflex routing architecture.
• Developing and optimizing software to drive performance improvements by leveraging innovative FPGA hardware features.
• Owning various modules of the routing and retiming engine, from device modeling to timing closure to runtime.

• Intellectual curiosity and a passion for exploring new technology.
• Excellent problem‑solving, debugging, and attention to detail.
• Great communication, teamwork, and interpersonal skills.

The pay range below is for Bay Area, California only. Actual salary may vary based on a number of factors including job location, job‑related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$200.4 – $290.1 USD

• Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• MS + 15 years of industry software experience, or Ph.D. + 10 years of industry software experience.

• Significant experience coding & hands‑on development of high‑performance multi‑core software systems.
• Extensive experience as an architect/technical lead for developing EDA/CAD routing algorithms for FPGAs.
• Proven leadership skills for collaborative cross‑functional projects.
• Experience with Altera® Quartus or AMD Vivado software.
• Experience with graph theory and network‑based optimizations including pathfinding and combinatorial optimizations.
• Experience with applying machine learning techniques to EDA software.

Regular

Shift 1 (United States of America)

San Jose, California, United States

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.