Sr. Software Engineer - NPU Compiler Solutions

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

AMD is looking for an influential software engineer who is passionate about improving the performance of key applications and benchmarks. You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology.

The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD.

• Contributing to the architecture and design of the MLIR-centric NPU compiler platform.
• Develop and integrate solutions to efficiently deploy algorithms on spatial compute devices, such as NPUs.
• Work with cross functional teams to identify problems and create solutions.
• Work with management team on project planning activities.

• Strong C/C++ systems programming (modern C++), Python for tooling/prototyping.
• Hands-on MLIR experience:
  Dialect design (ops/types/attributes/interface), Pass pipelines, (pattern rewrites, canonicalization/legalization). Proficiency with core dialects:
  Linalg/Tensor, Affine, SCF, Vector.
• Accelerator compiler experience: GPU/NPU/AI engines or similar spatial devices; memory hierarchies, streams, scratchpads, NoC-aware optimization.
• Auto-optimization: practical experience building or integrating auto-tiling, auto-scheduling, and auto-tuning systems.
• Operator fusion and graph-level optimization for DSP&ML workloads (CNNs, transformers, FFT), layout/dtype transforms, quantization-aware workflows.
• Solid understanding of heterogeneous runtime models, concurrency, synchronization, and performance profiling.

• Polyhedral/affine analysis, dependence analysis, bank/conflict modeling, memory placement strategies.
• Open-source contributions to LLVM/MLIR or peer-reviewed publications in compilers/ML systems.
• ML compiler stacks: IREE, TVM, XLA, Glow, Halide; auto-schedulers/tuners integration.
• Expertise in Linux kernel/driver development for multi-processor heterogeneous systems.
• Knowledge of Acceleration platforms like GPU, TPU, APU, FPGAs.

• Master's or PhD in Electrical Engineering, Computer Science, or related field.

• San Jose

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.