Analog Layout Engineer

This position requires - Clear Background, Drug Test, and Education Check.

Must be authorized to work in the US for any employer without Sponsorship.

(Principal Only! No Corp to Corp)

Position Title:

545055-Analog Layout Engineer

Location:

San Jose, CA
Pay Rate: $90-$100
Contract Duration: 6 months contract

• Layout of Analog / High Speed transceiver circuit blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. in a timely manner.
• Layout of sensitive active / passive components including resistors, capacitors and inductors.
• Design verification including DRC, LVS, ERC and ANT and extraction.
• Block level floor planning with design engineers.
• Review and update layout for quality including signal integrity, power integrity and parasitic.

• Associate degree or above with formal training in custom analog layout; BSEE or above preferred.
• 5+ years analog layout experience in deep sub-micron and FinFET processes.
• Experience in floor planning and layout of analog blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc.
• Solid knowledge in device structures.
• Understand tradeoffs in matching, coupling, parasitic effects, area, etc.
• Understand causes and preventions of ESD and latch-up.
• Proficient in interpreting verification DRC, LVS, ERC, ANT results.
• Working knowledge of Cadence Virtuoso and Mentor Calibre required.
• Team player with excellent communication skills.

We encourage Minorities, Women, Protected Veterans and Disabled individuals to apply for all positions that they may be qualified for. We maintain a drug-free workplace and perform pre-employment substance abuse testing and background checks.

If you are interested in this position, please submit your resume in a Word Document with the month and year that you have worked at each previous position to and copy: 545055-Analog Layout Engineer to the email Subject Line.

Job Posted Date: 3/10/2026