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Systems Engineer

Associate Design Verification Engineer - UVM SystemVerilog

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Millennium Software and Staffing Inc
Full Time position
Listed on 2026-03-12
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
A leading staffing and recruiting firm is seeking a Design Verification Engineer in San Jose, California. This role requires skills in UVM, UPF, VIP, System Verilog, VHDL, and SOC verification, with Python or TCL experience beneficial. The position is for contract employment aimed at Associate level candidates working in design-focused management. Ideal for those looking to enhance their expertise in a fast-paced technology environment.
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Position Requirements
10+ Years work experience
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