Sr. Staff Engineer, ASIC Design Automation - CAD

Sr. Staff Engineer, ASIC Design Automation - CAD

Location:

San Jose (on-site)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

We are looking for an expert Chip Design Automation Engineer to architect and maintain the design automation and methodologies for our high-performance ASIC/SoC team. In this role, you will lead the definition and deployment of automated design flows for complex ASIC/SoC that integrate digital logic, custom analog circuits, and photonics components in leading-edge process nodes.

As a Senior Staff Design Automation Engineer, you will lead the development of new automation capabilities, optimizing existing methodologies, bridging the gap between EDA tools and the physical design team, and problem-solving to ensure smooth tape-outs.

Key Responsibilities

* Flow Architecture:
Architect, develop, and deploy robust automated flows for Synthesis, Place and Route (P&R), Static Timing Analysis (STA), and Physical Verification using industry-standard tools (Cadence/Synopsys).

* Methodology Development:
Drive improvements in design methodologies, specifically for high-speed digital and mixed-signal integration, hierarchical design planning, and signoff, ensuring high reliability and ease of use.

* Tool Integration:
Manage the installation, qualification, and regression testing of EDA tools and PDKs for advanced process nodes.

* PDK & Tech Files:
Customize and maintain technology files (LEF, TF, MMMC setups, DRC/LVS decks) to ensure compatibility between digital (Innovus/ICC2) and custom (Virtuoso) environments.

* Automation:
Develop advanced scripts and wrappers (Python, Tcl, Make) to streamline design execution, data management, and quality of results (QoR) tracking.

* Flow Optimization:
Analyze and optimize flow performance to improve runtime, compute resource usage, and license efficiency; identify bottlenecks and implement software solutions.

* Support & Mentorship:
Serve as the primary focal point for resolving complex tool/flow issues and provide technical guidance to junior engineers.

Basic Qualifications

* BS or MS in Electrical Engineering, Computer Science, or related fields.

* 5+ years of industry experience in Chip Design Automation.

* Expert proficiency in scripting and automation using Python, Tcl, C-shell, and Makefiles.

* Deep understanding of the complete ASIC physical design flow (Synthesis, P&R, CTS, Routing, STA, and Signoff).

* Hands-on experience supporting major DEA tools (e.g., Cadence Innovus/Genus or Synopsys Fusion Compiler).

* Experience managing PDKs and technology files for advanced process nodes (5nm or 3nm).

* Proficiency with physical verification flows (Mentor Calibre, Synopsys IC Validator) and debugging rule deck issues.

* Experience with version control systems (Git, Perforce) and workload management.

Preferred Qualifications

* Experience developing Mixed-Signal flows (Open Access interoperability), bridging Cadence Virtuoso and digital P&R tools.

* Experience with PDK development (P-cells, techfiles) or customizing DRC/LVS decks.

* Experience with 3

DIC/Chiplet packaging methodologies and co-design flows.

* Background in photonics design automation or special custom circuit requirements.

* Proven ability to work with EDA vendors to track feature requests and debug software bugs.

Salary range: $170,000 - $223,000

Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship.

Veterans are more than welcome and encouraged to apply.