Senior DFT Engineer ASIC/SoC Test & Validation
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-03-12
Listing for:
Etched
Full Time
position Listed on 2026-03-12
Job specializations:
-
Engineering
Systems Engineer, Engineering Design & Technologists, Electrical Engineering
Job Description & How to Apply Below
A cutting-edge technology company in San Jose is looking for a highly skilled Design For Testability (DFT) Engineer. This role entails developing DFT architectures for ASIC designs and collaborating with cross-functional teams to ensure robust testing. Candidates should have over 10 years of DFT experience, proficiency in System Verilog, and a Bachelor’s degree in Electrical Engineering. The position offers competitive medical benefits, a housing subsidy, and a dynamic work environment focused on technological advancement.
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Position Requirements
10+ Years
work experience
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