Staff Engineer, Layout Design

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World's Technology Together

Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

Samsung Semiconductor Inc. (SSI) is advancing the world's technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

Samsung Semiconductor Inc. is looking for a talent that has a strong background and hands‑on experience on RF/Analog circuit layout design. The candidate will be developing next‑generation RF transceivers and mixed‑signal circuits for wireless communication systems along with circuit designers.

Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy

What You’ll Do

• Work with design engineers to come up with an optimal floorplan in terms of area and performance.
• Be able to lead a few layout engineers, help them plan, and execute on layout tasks to accomplish complicated layout blocks.
• Finish layout tasks with good quality.
• Have good communication skills to collaborate with other design and layout engineers.
• Track schedule and status regularly to make sure the layout will be finished on time.

What You’ll Do (continued)

• Working with remote circuit designers to determine the chip floorplan and develop strategies to optimize the parasites, reduce area, and improve high‑speed SERDES/analog performance.
• Estimate schedule and develop a plan to get things done within a dedicated time frame.
• Read the design document provided by the foundry and resolve issues like latch‑up and DRC.
• Perform custom layout using Virtuoso, and obtain LVS/DRC clean results.
• Be familiar with CAD tools, including Virtuoso, Calibre LVS, DRC, Skill Cad, and related tools.
• Desire experience on chip‑level design, such as bump, pad, and ESD strategies.
• Maintain good communication skills to discuss with circuit designers.

What You Bring

• Bachelor's Degree with 10+ years, Master’s with 8+ years, or PhD with 5+ years of relevant industry experience in Electrical Engineering, Technical, or related field preferred.
• Extensive experience in analog/mixed‑signal layout design of deep‑submicron CMOS circuits and recent experience on advanced nodes including FinFET technologies.
• High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS reports.
• Extensive experience in analog/RF related circuit layout, including LNA/PA/PLLs and others.
• High level of proficiency in CADENCE or MENTOR GRAPHICS layout tools.
• Good communication skills with design leads and engineers for schedule planning.
• Ability to lead a small group of layout engineers to deliver a successful tapeout.
• Programming knowledge in SKILL, Perl, and/or Python is a bonus.
• Inclusive mindset, adapting your style to the situation and diverse global norms.
• Avid learner, approaching challenges with curiosity and resilience, seeking data to build understanding.
• Collaborative, building relationships, humbly offering support and welcoming new approaches.
• Innovative and creative, proactively exploring new ideas and adapting quickly to change.

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What We Offer

The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role's function and location, as well as the…