Sr. STA Engineer

Job Details

Job Description:

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings.

We are seeking a highly skilled and hands‑on Timing Doer to join our full‑chip timing team. This role is critical to achieving top‑level timing closure for complex SoC/ASIC designs. The ideal candidate is a technical expert in STA, scripting, and timing infrastructure, capable of driving timing accuracy, automation, and scalability across the full chip.

• Run and maintain top‑level timing analysis across all modes and corners using tools like Primetime.
• Ensure every path is timed correctly; track and improve timing quality metrics such as coverage, margin distribution, and skew.
• Maintain and update STA tool versions and patch releases; seamlessly roll out PVT corner changes and scaling methods for unsupported libraries.
• Develop robust scripts (Tcl, Python, shell) to automate STA runs, report generation, ECO flows, and environment setup; create scalable and reusable infrastructure for timing tasks.
• Implement scaling techniques for missing libraries; rapidly adjust PVT corners and integrate changes into the flow.
• Work closely with timing owners and block teams to resolve cross‑boundary timing issues, provide infrastructure and tooling support, and ensure timing signoff criteria are met across all corners and modes.
• Validate timing post‑ECO and post‑layout; collaborate with the clocking team and other backend full‑chip designers for clocking balance, timing fixes, power delivery, and partitioning.
• Collaborate with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validate high‑performance low‑power clock network guidelines.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

• Bachelors in Electrical Engineering, Computer Engineering, or STEM field with 9+ years or Masters Electrical Engineering, Computer Engineering, or STEM field & 6+ years or PhD Electrical Engineering, Computer Engineering, or STEM field & 4+ years of industry experience.
• 7+ years of industry experience in Complex CPU/SOC/ASIC/FPGA implementation and timing closure.
• 5+ years in STA signoff tools like Prime Time, Constraint generation and verification tool like Fishtail.
• 3+ years scripting skills in TCL/Python/Perl/Shell.
• 3+ years of RTL Design Development and physical implementation.

• Strong expertise in Static Timing Analysis (Primetime, Tempus, etc.)
• Proficiency in scripting languages:
  Tcl, Python, shell.
• Deep understanding of PVT corners, library modeling, and timing abstraction.
• Experience with timing ECOs, report analysis, and flow automation.
• Ability to manage and scale timing environments across large designs.
• Excellent problem‑solving and debugging skills.
• Strong communication and collaboration abilities.
• Experience in full‑chip timing closure for advanced SoC/ASIC nodes.
• Familiarity with hierarchical STA and timing model generation.
• Knowledge of physical design flows and layout impact on timing.
• Exposure to version control systems and CI/CD for EDA environments.

Experienced Hire.

Shift: Shift 1 (United States of America). Primary

Location:

Virtual US. Additional Locations:
Business group:
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