Senior OSAT Engineer

Altera  .Senior OSAT Engineer page is loaded## Senior OSAT Engineer locations:
San Jose, California, United Statestime type:
Full time posted on:
Posted Yesterday job requisition :
R01840#
** Job Details:**### ##
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* Job Description:

**** About Altera
** Altera is a global leader in FPGA and programmable logic solutions, enabling innovation in data center, communications, automotive, aerospace, and industrial markets. As we expand manufacturing capabilities for next-generation programmable devices, we are strengthening our OSAT engineering organization to deliver world-class backend manufacturing performance.
** Role Summary
** We are seeking a highly skilled
** Senior OSAT Engineer
** to drive outsourced assembly and test engineering activities across Altera’s global supplier network. You will lead NPI readiness, yield optimization, cost improvements, and qualification activity for packaging and test flows supporting Altera’s FPGA/SoC product lineup. This role requires strong semiconductor backend engineering experience, hands-on problem solving, and the ability to collaborate closely with OSAT partners and cross-functional stakeholders.
** Key Responsibilities
*** Lead technical engagement with OSAT suppliers on assembly and test process development, yield ramp, quality improvement, and volume manufacturing readiness.
* Drive new product introduction (NPI) from engineering builds through production release, ensuring OSAT capability meets electrical/thermal/mechanical requirements for FPGA and SoC products.
* Optimize packaging and test architectures for performance, cost, and reliability: flip-chip BGA, high-pin-count packages, substrate technologies, wafer-level solutions, burn-in/FT coverage.
* Monitor and improve backend yield performance using data-driven analysis; identify systemic issues and lead root cause / corrective actions.
* Partner with Test Engineering, Packaging, Product Engineering, DFM, and Quality teams on process optimization, failure analysis, and manufacturability improvements.
* Implement and maintain process control systems, SPC methodologies, automation improvements, and lean manufacturing principles at OSAT.
* Support cost reduction initiatives including BOM optimization, process simplification, and cycle time improvements.
* Track supplier performance metrics (yield, DPPM, cost, cycle time, OEE) and provide updates with risk assessments and mitigation plans.
* Lead or support reliability testing and package qualification activities aligned to industry standards (JEDEC, IPC, AEC-Q).
* Maintain strong technical relationship and communication cadence with OSAT partners to ensure transparency, collaboration, and escalation management.
** Salary Range
** The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$159,700 - $231,000 USD
** We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.### ##
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* Qualifications:

**** Minimum Requirements
*** Bachelor’s degree in Electrical Engineering, Materials Science, Mechanical Engineering, or related field.
* 10+ years of semiconductor assembly, packaging, or test engineering experience.
* Hands-on experience with OSAT manufacturing environments, including wafer finishing, substrate attach, interconnect packaging, test, and burn-in.
* Strong technical understanding of backend manufacturing flows: flip-chip, wire bond, underfill, molding, final test, reliability stress and analysis.
* Proven ability to analyze yield, reliability, and cost data to drive engineering decisions and improvements.
* Demonstrated success working with international suppliers and cross-functional teams.
* Strong written and verbal communication skills, including technical reporting and supplier engagement.
****** Preferred Qualifications
*** FPGA, ASIC, or SoC backend experience, particularly high-pin-count or high-power devices.
* Experience in…