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Senior Analog​/Mixed-Signal Verilog Modeling Engineer

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Broadcom Inc.
Full Time position
Listed on 2026-01-15
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading technology company seeks an Analog/Mixed Signal Verilog Modeling Design Engineer to develop models for various analog IPs and work closely with design teams. Candidates must have at least 8 years of experience, proficiency in System Verilog, and knowledge of analog circuits.

This role offers a competitive salary and a comprehensive benefits package, promoting an inclusive work environment.
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Position Requirements
10+ Years work experience
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