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SoC Logic Design Engineer

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Altera
Full Time position
Listed on 2026-01-14
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below

Job Overview

Accelerating Innovators – Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system-on-modules, Smart

NICs and IPUs, offering the flexibility to accelerate innovation.

Job Details

Title: SoC Logic Design Engineer

Job Type: Regular (Full-time)

Shift: Shift 1 (United States of America)

Primary

Location:

Austin, Texas, United States

Additional Locations: San Jose, California, United States

Key Responsibilities
  • Develop RTL designs for SoC integration, ensuring efficient and optimized logic implementation.
  • Participate in defining architecture and microarchitecture features of designated blocks.
  • Conduct thorough quality checks across various aspects of logic design, including RTL validation, timing, and power convergence.
  • Apply advanced strategies, tools, and methods to optimize RTL for power, performance, area, and timing goals.
  • Ensure verification plan and implementation correctly validate design features.
  • Identify and resolve RTL issues to maintain design integrity and compliance with security best practices.
  • Work closely with IP providers to integrate and validate IPs at the SoC level.
  • Ensure smooth IP-SoC handoff through rigorous quality assurance compliance.
Qualifications
  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
  • Minimum 7 years of experience in integrating ARM advanced cores and related ARM IP.
  • Strong expertise in coherent interconnect design and integration.
  • Proven experience as an SoC integrator, handling complex SoC-level integration tasks.
  • Demonstrated experience as a lead micro-architect in SoC design.
  • Knowledge of Design for Test (DFT), physical design, and verification methodologies.
  • Proficiency in static timing analysis and optimization.
  • Strong understanding of security best practices in hardware design.
Salary Range

$181,100K - $289,300K USD

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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